
GD32F103C8T6
The GD32F103xx device is a 32-bit general-purpose microcontroller based on the ARM CortexTM-M3 RISC core with best ratio in terms of processing power,reduced power consumption and peripheral set.

The GD32F103xx device is a 32-bit general-purpose microcontroller based on the ARM CortexTM-M3 RISC core with best ratio in terms of processing power,reduced power consumption and peripheral set.

The LPC11A14FBD48/301 is a 32 bit ARM Cortex M0 microcontroller with 32 kB flash and 8 kB SRAM and 4 kB EEPROM MCU.

The STM32L010K8T6 is a 32-bit ARM-M0 core microcontroller (MCU) with 64kb flash memory and 8kb Ram.

The MCF51AC256ACLKE is a 32 bit variable-length RISC Microcontroller MCU with 256 kB flash.

The STM8AF5268TAXis automotive 8 bit microcontroller MCU with up to 128 kb Flash.

The ZOE-M8Q-0-10 GPS positioning chip is a fantastic innovation in the world of technology. It is an ultra-small SiP that is designed to pack a punch in terms of functionality, without taking up

The STM32F405xx and STM32F407xx family is based on the high-performance ARM®Cortex®-M4 32-bit RISC core operating at a frequency of up to 168 MHz.It have ARM Cortex-M4 32b MCU+FPU, 210DMIPS, up to

The AVR128DA28/32/48/64 microcontrollers of the AVR DA family are using the AVR CPU with hardware multiplier, running at up to 24 MHz, with 128 KB of Flash, 16 KB of SRAM, and 512B of EEPROM in 28-,

The STM32F103xx medium-density performance line family incorporates the highperformance ARM Cortex™-M3 32-bit RISC core operating at a 72 MHz frequency, highspeed embedded memories (Flash memory up

Features • Core: ARM® 32-bit Cortex®-M0 CPU, frequency up to 48 MHz • Memories – 16 to 256 Kbytes of Flash memory – 4 to 32 Kbytes of SRAM with HW parity • CRC calculation unit • Reset and power

Features Core 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline Extended instruction set Memories Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C

SAK-TC277TP-64F200N DC belongs to the TC27xT family . Its innovative multicore architecture, based on up to three independent 32-bit TriCore CPUs, has been designed to meet the highest safety