Key Features
Device Family: MAX V
Device Type: CPLD (Complex Programmable Logic Device)
Logic Elements (LEs): 80
Macrocells: 80
User I/O Pins: 54
Embedded Memory: 2 Kbits (User Flash Memory)
Configuration Type: Non-volatile (Flash-based, instant-on)
Operating Voltage: 1.8 V core, 1.7 V–3.6 V I/O compatible
Power Consumption: Ultra-low static power (typical < 50 µA in standby)
Package: 64-pin EQFP (E64) – 10 mm × 10 mm
Speed Grade: –5 (typical system frequency up to 150 MHz)
Operating Temperature: 0 °C to +85 °C (Commercial grade)
JTAG Programming: IEEE 1149.1 compliant
Security: Programmable protection for design security
Endurance: > 1000 program/erase cycles
Performance Highlights
Instant-on capability: Device powers up and configures in < 1 ms
On-chip flash memory: Retains configuration even when power is removed
Low static and dynamic power: Ideal for battery-operated or always-on systems
Flexible I/O standards: Supports LVCMOS, LVTTL, and open-drain I/O
Integrated User Flash Memory (UFM): For small data storage or ID codes
Applications
Power sequencing and reset control
Interface bridging and logic replacement
Configuration management for FPGAs or MCUs
Industrial control and instrumentation
Portable and embedded systems
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